Kenji Ishimaru – [Ishimaru Information Engineering Office]
About 25 years, I work in the embedded system design field. I provide responsive, cost effective engineering services and solutions for embedded system development from system architecture to small module design.
- The Institution of Professional Engineers, Japan
- Web Analytics Consultants Asssociation
- Information Processing Society of Japan
-Embedded Computer System Development
Developed 2D/3D graphics computer systems for Arcade Game.
Verified and debugged Engineering Sample ICs (ES) on computer boards by using Logic Analyzer.
- Developed low-power, complex math operation RTL modules for ASIC by SystemVerilog.
- Planned 3D graphics IP Core system architecture to satisfy required features, gate size and production schedule.
- Invented the lighting algorism for real-time 3D graphics to generate photo realistic scene image.
- Invented image compression algorithm suitable for real-time image decoding.
Functional Verification/Hardware Emulator
- Built SystemVerilog verification environment with random data generation, assertion, and functional coverage.
- Improved ASIC verification time by porting the designs from RTL simulation environment to a hardware emulation system environment.
- Evaluated the performance of the hardware emulation system to be introduced when multiple designs shared emulator resources simultaneously.
- Planned ASIC functional evaluation strategy and implemented on RTL simulation environment.
- Planned and built functional verification environment for RTL designs by using black-box, white-box and gray-box testing methods, implemented by hardware verification language (e language).
- Verified standard interfaces (PCI, USB and AMBA AHB) with e verification language.
- Instructed e verification language methodology to HDL designers of customer companies.
- Built the Japanese FAQ web site of e verification language for Japanese HDL designers.
- Built processor systems with the designs under test on FPGA based-prototyping systems for robust RTL verification, early software development and IP Core demonstration.
- Improved middleware development time by building FPGA based-prototyping system before actual ASIC production.
Open Source Project
USB Host C Library
Open Source C library for FPGA based USB host. The C library provides APIs to control USB HID(Human Interface Device) class device and Mass Storage class device.
3D Graphics IP Core
Wire-Frame 3D Graphics IP Core for small size FPGA.
3D Graphics Rendering System.
FPGA Magazine (CQ Publishing Co.,Ltd.)
DVI implementation for ZedBoard and DE0-nano-SoC
AXI Performance Comparison, Cyclone V SoC and Zynq
USB Communication Target Device
USB Communication Target Device http://www.kumikomi.net/fpga/sample/0012/FPGA12_092.pdf
USB Communication Device Class
Project Porting from DE0 to DE0-nano
USB storage device with FAT file system
USB Full-Speed Host System – Hardware Part –
Interface (CQ Publishing Co.,Ltd.)
Open source Ethernet IP Core and Open source TCP/IP protocol stack
USB Full-Speed Host System – How to use USB host library –
USB Full-Speed Host System – Programming, initialization and main loop –